Metastability is different from what we normally mean with "unknown" for a digital signal ('X' in simulation).
It is when the output from a flip-flop/register settles later than normal due to a setup/hold violation.
The flip-flop/register becomes "analog" during the extended settling time, with possible signal levels somewhere in-between '0' and '1'.
If you feed an unknown but not metastable signal to both inputs of a 2-input XOR gate, the output is '0' (in the real world, maybe not with an 'X' input signal in simulation).
If you do the same with a metastable input signal, the output is unknown because one input may see it as '0' and the other may see it as '1'. The output can be '0', '1', can have glitches or be in-between like the metastable input.
If you have '1' to one input of an AND gate, and the other input is metastable, the output is truly "unknown".