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They are usually confidential, so you probably can't find them online easily. Even if you do you and the ones that are sharing it are infringing the agreement.
So the issue is that polysilicon is not a very good conductor and we usually try to avoid making huge gates. So instead of creating a milimeter long gate we usually divide it into sub units called fingers. And these fingers can be placed in a way to reduce the total area and parasitics. This placement is making them share drain or source with the next piece of gate.
Width can't be larger because the fab can't guarantee that the MOSs with your parameters would work up to spec. So they don't allow it but you can do it, they just wouldn't take responsibility. There should be a hard constraint switch in TSMC models, if you uncheck that it should allow.
Number of fingers is technically unlimited, but again that might be another rule I'm not aware of.
For quick reference, diffusion areas at the edges are 0.48 um long and width of the transistor wide. Diffusion areas for shared source/drains are 0.54 um long and width of the transistor wide. But it should calculate these values itself. I don't know why it's not doing it.