Hi,
i just went through both of the links but neither of them answers gmish's question.
A sequential circuit is compromised by a set of memory elements (FFs, Latches, Combinational Gates with Feedback) and combinational logic.
If during design time you know exactly the possible value combinations that the memory elements will get, you have an FSM.
When the memory elements take arbitrary values during circuit operation (the better way to think of this scenario is the memory elements being the registers of a processor's pipeline)
you make the assumption that all value combinations of the memory elements may happen.
Now, with respect to optimization of the FSM circuits, there are a lot of scenarios which simplify the logic.
If a combination that you thought it was possible to happen, never happens, then an unreachable state is found and it can be used for Logic Simplification.
If two value combinations (sequential system states) can be merged to a single one without affecting system's operation, a redundant state is found, further
optimizing the circuit.
etc. etc.
Pavlos