What is the most error of tape-out?

[stormwolf]

After tape-out may have some error, now i want to know what is the most frequence error after tape-out.
1. function error
2. timing error
3. signal intergrate
4. don't know
thanks!

 

[mediatek]

1. glitch(cannot found in FPGA)
2. timing(simulation/AE testing not complete , logic/model error ... )
3. leak current , floating signal , power consumption not as expected.

 

[diablo1222]

If your design is full digital , the most error maybe is timing error. But if your design is mix-singal design, it is function error.

 

[Evo]

power consumption is the most critical things for IC design and it is the most commonly see error after tape-out.

i have another experience that my designers reluctanted to use foundry provided black box ESD protection circuit (because it is too huge) and they designed the ESD protection circuit by their own, unfortunately after tape-out, i found out that the ESD protection was not up to the expectation. therefore we had to re-tape out.

 

[xiaolongbao]

i think maybe short of power--groud is serious!

 

[gogogo]

o, i aree with xiaolongbao,,
it occured at our chip!!!!!!!

 

[wangkl]

The most stupid mistake I've seen is that,
we purposed to embed 128kbytes ram in our chip,
but somebody implemented 128000 byte ram.

 

[Evo]

what is the different between 128KBytes and 128000Bytes?

mmh... it should be 128x1024byte...

 

[atremp]

Timing, especially the DFT hold timing double check

 

[troops]

where can i get more info about this ????

 

[FLEXcertifydll]

You do the right chip.

 

[power-twq]

I think the most error is IO interface timing error.

After tape-out may have some error, now i want to know what is the most frequence error after tape-out.
1. function error
2. timing error
3. signal intergrate
4. don't know
thanks!