dechenxu
Newbie level 6
In the VHDL langguage, the std_logic type has 9 states including "weak high",
"weak unknown","weak low",etc. And i dont know the differences between "weak high" and "forcing high","weak low "and "forcing low" ,"weak unknown" and "forcing unknown". Can anyone help me? thank you!
dechenxu
"weak unknown","weak low",etc. And i dont know the differences between "weak high" and "forcing high","weak low "and "forcing low" ,"weak unknown" and "forcing unknown". Can anyone help me? thank you!
dechenxu