In the VHDL langguage, the std_logic type has 9 states including "weak high",
"weak unknown","weak low",etc. And i dont know the differences between "weak high" and "forcing high","weak low "and "forcing low" ,"weak unknown" and "forcing unknown". Can anyone help me? thank you!
dechenxu
in digital design, we have logic states {1,0,z,x}
which correspond to {5v,0v,z,(1.8-3)v} respectively.
in std_logic, we interpret the values (1.5-2.2)v as weak-zero. same explanation follows for the others also.
we usually come across these logic states only when you are working with some communication circuits.
else where, the standard states {1,0,z,x} will suffice.