What is the maximum ratio of current gain that can be achieved using a current mirror? Or in other words what is the maximum ratio of the transistor geometries that is possible with a current mirror?
Is there an upper bound on the current gain to start with and if there is then why?
Current mirror multiplication is multiplying the device/width mismatch too. The higher the current multiplication by current mirror is, the more process variation is affecting the accuracy of output current.
One thing is that the bias voltage dictates your current. So,the current mirroring is form a replication using the same gate voltages and increasing the width ,changes the current. If you are designing one such thing,start of with a Vdsat = 250 mv. No one can say ,just a number for ratio,as it depends on the specification, like the allowed capaciatance at that node etc.
I have another question here. Let's say I need a current mirror ratio of 2:3. I determine the number of fingers of each transistor as 4:6 so that I could use interdigitized form of layout. Someone mentioned to me that the W of each fingers used should be less than 20um for 0.35um process. How true is this and what's the rationale behind it? Thank you.