# What is the maximum ratio of current gain that can be achieved using a current mirror

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#### assembly

##### Newbie level 4 What is the maximum ratio of current gain that can be achieved using a current mirror? Or in other words what is the maximum ratio of the transistor geometries that is possible with a current mirror?

Is there an upper bound on the current gain to start with and if there is then why?

Thanks

#### jlee

##### Member level 2 Re: Current Mirrors

Current mirror multiplication is multiplying the device/width mismatch too. The higher the current multiplication by current mirror is, the more process variation is affecting the accuracy of output current.

#### paulux Re: Current Mirrors

Since the ratio of current mirror is governed by the geometric size, this is limited physical limitation on the sizing accuracy.

#### hanjiemy

##### Member level 2 Current Mirrors

20

#### assembly

##### Newbie level 4 Re: Current Mirrors

Why 20? What is the logic behind it?

Thanks

#### krrao

##### Junior Member level 2 Re: Current Mirrors

Current mirrors has a physical limitations.

If the length of the mirror is more , then there will be a change in current values due to large paths

#### avlsi

##### Member level 3 Re: Current Mirrors

One thing is that the bias voltage dictates your current. So,the current mirroring is form a replication using the same gate voltages and increasing the width ,changes the current. If you are designing one such thing,start of with a Vdsat = 250 mv. No one can say ,just a number for ratio,as it depends on the specification, like the allowed capaciatance at that node etc.

#### bsrivastava

##### Member level 2 Re: Current Mirrors

I used it x10 factor with 99% efficiency. 250 uA to 2.5 mA

#### pseudockb

##### Member level 5 Re: Current Mirrors

I have another question here. Let's say I need a current mirror ratio of 2:3. I determine the number of fingers of each transistor as 4:6 so that I could use interdigitized form of layout. Someone mentioned to me that the W of each fingers used should be less than 20um for 0.35um process. How true is this and what's the rationale behind it? Thank you.

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