Max frequency at which the logic can work after synthesis. The final value depends on the amount of logic and the FPGA. It is normally mentioned either in frequency or delay.
Yes, maximum frequency depends on the logic in the FPGA.
You can know it in the timing analysis report generated after place and route is completed.
The maximum working frequency depends on the delay of the combo logic between two flops.
Generally while selecting the device, fpga freq is one of the constraint. Also, as we move on from spartan to vertex family of xilinx, we see higher frequency support and "fpga frequency" would be higher.
I wanted to ask what is this fpga fequency mean and where to find information on that.
generally frequency given will be the frequency of the external clock ... Now this clock is given to the DCM or PLL of the FPGA from which frequency can be either increased or decreased...
did you mean how fast the outputs on the FPGA are produced or the frequency of its clocks? for the clocks, it depends on the kit you have of course and it's going to be in the datasheet...for the design itself it appears in the timing report in ISE...by the TRACE tool...
Actually there are 2 things here:
One is: how fast an fpga may work i.e what is the max frequency an FPGA may be able to work at. may be at this point of time there may not be any logic between registers, say for example a shift register. This is the capability of the FPGA to work at a clock rather than the capability of a design working inside FPGA.
For example : An FPGA may have a spec that it can work on clock frequencies up to say 500Mhz. This spec must be provided by the FPGA vendor.
Second is: How fast a design when put in FPGA may work at: well that depends upon the kind of design you put in.
Hope it helps,
Kr,
Avi
Maximum frequency of operation of your design is given by synthesizer report.
If not obtained, recheck constraints, or design.
Every FPGA got a maximum operating frequency, which is very high. This is different from operating frequency of your project. Your design is not going to work on a frequency specifed by the FPGA vendor.