IR drop
IR Drop as said above is voltage drop from the PAD circuitry to the standard cells.
> The implication is the reference voltage VDD is different at different places in the chip causing on chip variations . Also, a ngative impact on timing due to reduced VDD => (Vdd - I*R)
> To keep the IR drop (voltage drop) within a particular range, we generally do power planning, by deriving
- the number of core power pads
- the core ring width
- the core straps (Mesh) width & spacing & number
#REF: Power Network Design For an ASIC with
Peripheral IO Power PADs (Solvnet) for detailed calculations
Note: This Power Planning is effectively nothing but Kirchoffs Current Law.
Cheers