What is the inter and intra delay in Verilog?

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ananth_anbu

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verilog question

Hi,

what is inter delay and intra deay in verilog? ple explain?
 

Re: verilog question

They are similar to inertial delay and transport delay in VHDL respectively.
Check VHDL book Perry for the explnation.
 
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    ananth_anbu

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Re: verilog question

Inter Assignment Delay is most commonly used delay
It simply wait for appropriate no of timesteps before executing the command.
#10 q = x + y;

Intra-Assignment Delay (Used in data flow modelling)
q = #10 x + y;

The value of x+y is stored at the time that the assignment is executed, but this value is not assigned to q until after the delay period.
 
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verilog question

Check Verilog book by Samir Palnitkar. It is given quite nice in that
 

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