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Re: what is the inputs and outputs of the placement and CTS
Hi,
For the placement the inputs are the design with completion of floorplan and power routing, placed I/Os and placed memory macros(if any). The output is completely legally placed design, you can analyze the timing, power, slew etc.
For cts, clock specifications like skew, insertion delay limits etc and the placed design database are the inputs. Output is clock routed design. You can analyze the skew, timing, insertion delay, power etc reports.
Re: what is the inputs and outputs of the placement and CTS
Placement Inputs:
• Floorplan(Macro Placement, IO placement & Power Routing) done database.
• SDC file ( If you want to do the placement based on the timing information)
• CTS Tech File (If you want to do the placement based on the Clock information)
• Preserve Inst file ( Some Instance we may need to place manually to achieve better timing, so those inst are need to set don’t touch attribute)
Placement Outputs:
• Placement done database
• Timing Analysis reports ( Pre-CTS Timing Analysis)
• Some more reports based on various violation checks related to placement of the std cells.
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