what is the importance of clock enable signal?

Hi everybody

I have a statistical question about the application of clock enable signal. I want to know How many percent of applications connect the clock enable to a fixed active voltage level (and what are some of these applications?) and How many percent of applications connect the clock enable to a varying signal (and what are some of these applications?)?

Thanks by advance

Added after 5 hours 13 minutes:

The above questions may seems meaningless!
but suppose we want to design a logic element for an fpga.
we have a register with a clock enable signal and want to decide about the possible sources that can drive this signal.
one possible solution is to connect output of a 2 to 1 multiplexer to clock enable
so that data inputs of mux come from external sources.
an other possible solution is to connect output of a 2 to 1 multiplexer to clock enable
so that one of it's data inputs is connected to VDD and the other one comes from an external source.

Hi bigdogguru
No. this is not a rhetorical question.
Infact I want to choose one of the mentioned solutions by a strong statistical reason.
if for example at 60% of application the clock enable is connected to a fixed active voltage level then it is better
to choose the second solution because it consumes little routing sources of FPGA.