What is the frequency of the CCLK generated in master mode?

[shivams]

what is the frequency of the CCLK generated in master mode?

 

[farhada]

configuration clock

What device? Xilinx?

 

[TA37]

configuration clock

This will probably depend on the family of part. I know that Xilinx actually lets you specify in the bitstream. It will go to some slow 1-4MHz default till it reaches the bitstream command that sets the rate for the rest of the bits.

 

[farhada]

Re: configuration clock

This is for the old devices:

FPGAs have optionally controlled CCLK speeds. XC4000 devices
can generate a configuation clock (CCLK),used to clock
configuration data to the device when operating in master mode,
at two different speeds. In the default slow mode, frequency
ranges from 0.5MHz to 1.25MHz In FAST CCLK mode, the frequency
will range from 4MHz to 10MHz. The XC4000X family FPGAs can run
as fast as 15MHz when in fast mode.

It was also sent on Xilinx discussion forums:

the frequency of CCLK in master mode is determined by your bitgen settings when you biold the bitstream. The clock starts out at the

default, 2.5 MHz IIRC, and when the frequency selected by bitgen has been transferred to the part, the CCLK frequency changes. Note that it is

possible to request CCLK frequencies higher than the capability of the XCF prom, and you need to use the maximum CCLK frequency when determining

your highest usable clock speed, not the nominal frequency selected for bitgen.

I am sure for this kind of questions, you better off getting to their site rather than here.

http://forums.xilinx.com

Hope it helps,

Cheers,
Farhad Abdolian