Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
basically a series inductance and resistor and a parallel (branch to GND) capacitance. Depends on your circuit which elements must be considered. For a power supply bypass capacitor connected through 1 or 2 vias, mainly the unwanted inductance counts, for a high impedance circuit, the few tenths of pf could be an issue. For a transmisson line, you can design one or more vias to match the impedance, effectively eliminating the via influence.
I don't agree, that vias always should be minimized. As an example you can see arrays of via in some designs instead of one, either for higher current capacity or thermal purposes.