What is the effect of clock gating in design?

[anishjp]

Hi all,
What is the effect of clock gating in design.....?

 

[AdvaRes]

Re: Clock Gating

Hi all,
What is the effect of clock gating in design.....?

It is a low power techniques. What do you mean by effect ?

 

[phoenix_pavan]

Clock Gating

It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.But, a latch implementation is widely used to avoid glitches

 

[anantha_09]

Re: Clock Gating

>>>>>It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.***But, a latch implementation is widely used to avoid glitches *****

latches are prone to glitches coz of enable being high.
F/F avoid glitches

Added after 18 seconds:

>>>>>It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.***But, a latch implementation is widely used to avoid glitches *****

latches are prone to glitches coz of enable being high.
F/F avoid glitches

 

[flatulent]

Re: Clock Gating

One thing to avoid is using a gating method that will produce a pulse below the minimum required to clock the following circuits. Some will clock and some will not which will put your system into an indeterminate state.

 

[vlsi_eda_guy]

Re: Clock Gating

DFT is another thing to consider when doing clock gating..

-cheers
vlsi_eda_guy

 

[badola]

Re: Clock Gating

For gated clocks or derived clocks: a test mode should be implemented that will driveall the Flip-Flop (FF) clocks from a single test clock during this test mode. Also, clock skew for this test clock should be properly balanced so there are no hold violations on any of the registers both during scan shift and normal mode.

 

[anishjp]

Re: Clock Gating

Hi all,
What is the effect of clock gating in design.....?

It is a low power techniques. What do you mean by effect ?

Hi AdvaRes,
Thanks for the reply, Can u explain me how it saves power...?

 

[AdvaRes]

Clock Gating

Hi anishjp,
It's quite simple. Suppose that you have a system composed of differents sub-systems which are clocked with the same or differents clocks CLK1, CLK2.....
In some case/application some sub-systems are not used all the time so we swich them of by desabling their corresponding clocks. This saves power since it woould no longer be a consumed dynamic power becase transistors of this subsystem does not switch.

Hope it helped !

 

[aru_vlsi]

Re: Clock Gating

It is basically used to save the Dynamic Power in the design.

Clock gate can consist of some gate(AND/OR/NOR/NAND) and a latch. This is called discrete clock gating.

It may be present in the library as a single entity.That is called Integrated Clock Gating.

Discrete is prone to glitches whereas the later one is free from glitches.

:idea:

 

[alpeshchokshi]

Re: Clock Gating

clk gating is used for power saving... at the same time in DFT its required for testmode and normal mode.

 

[newcpu]

Clock Gating

Glitches can be avoid by using ICG cell in the library.

 

[sudheerprasad]

Clock Gating

lets assume a FF is feeding a combinational block ,as long as the o/p of FF remains the same the combinational block wont switch bcoz its inputs are constant,so how come clock gating saves power?

 

[skyfaye]

Re: Clock Gating

Backend tool (Synthesis & PAR) does not handle clock-gating too well.

 

[thiery]

Re: Clock Gating

Clock gating saves power in both the clock tree buffers (which stop switching), and in the clock tree leaf cells (Flipflops).

Backend tools handle clock gating automatically during and after CTS (CTS being CG aware, and clock gating timing checks being applied after CTS), and you can declone and clone clock gates to optimise them in the Physical Implementation stages if required.
There can be issues with the relative timing of the enable signal at the clock gate with respect to the clock, which you will only see this after CTS. These occur if the clock gates are a long way up the clock tree, if there is large skew (between the enable signal source ff and the gated ff), or if there is a lot of logic leading to the enable signal. This can be dealt with by standard timing optimisation after CTS, or by cloning clock gates before CTS. Alternatively once you know the size of the violations you can push this information back into synthesis, using set_clock_gating_check to model this, so that the enable path optimisation is done in synthesis for the next (Synthesis/PnR) itteration.

You also need to be aware of the effect of the clock gating on the reset process.
If you are using asynchronous resets then there will be no issue with resetting the design.
If you are using synchronous resets, then you can run into problems with resetting the design, since the reset will only have an effect if the clock is reaching the flip-flops. In this case you would need to ensure that the enable conditions of the clock gates are enabled by the reset process (to pass the clock), and that you ensure that the reset is held for enough clock cycles to guarantee that all of the clock gating cells pass the clock, espcially if you have multiple stages of clock gating.
Probably easier to use asynchronous resets when using clock gating.
Ultimately you will need to verify the reset process with gate level simulation.