What is the diffrenece between timining analysis for FPGA and ASIC

Status
Not open for further replies.

omar-malek

Member level 5
Joined
Mar 24, 2007
Messages
89
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
French
Activity points
1,949
What is the diffrenece between timining analysis for FPGA and ASIC

so an engineer of digital design choice between timing analysis of fpga and asic .

the same for the constraint.?
thank you
 

First: The constraint concept is the same. Such as you need constraint clock period, identify false path, identify multi-cycle path, define input/output delay.
While each tool has different timing constraint syntax.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…