what is the diffirence between bit and std_logic In vhdl?

[ymq8328]

std_logic in vhdl

what is the diffirence between bit and std_logic In vhdl?

 

[omara007]

vhdl std_logic resolve

bit type can only represent : '0' or '1'

while type std_logic can represent things like :
'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care

 

[ymq8328]

std_logic *.pdf

I see. but why people prefer std_logic to bit,

 

[nand_gates]

vhdl resolve std_logic

std_logic is resolved when there are multiple drivers to a signal!
Whrereas in same situation bit generates ERROR!

 

[dBUGGER]

Re: what is the diffirence between bit and std_logic In vhd

Hi,
go through this pdf. You will understand.

Best Regards,

 

[wolfheart_2001]

Re: what is the diffirence between bit and std_logic In vhd

std_logic can help u in optimization process while sysnthesis in some situation if u used the dont-care . also std_logic give u more high-impedance value where u cant get with bit.

 

[SkyHigh]

Re: what is the diffirence between bit and std_logic In vhd

ymq8328,

but why people prefer std_logic to bit,

It depends.

For ALU and data path components such as registers, adders and multipliers, bit is good enough.

For bus, FSM control signals and intermodule signals, designers prefer to use std_logic to resolve logical issues.

As someone already said, std_logic offers 8 representations instead of ideal ones from bit.

You try to think about this scenerio,
"If you drive a logic over a bus or a lengthy wire, do you expect ideal 1's and 0's?"
This is why std_logic comes into the picture to resolve issues like this.

 

[omara007]

Re: what is the diffirence between bit and std_logic In vhd

I see. but why people prefer std_logic to bit,

You will definetly need to use std_logic in case you want to things like high impedance which is common with buses for example .. u may also need to express don't care and unchanged .. these things can't be expressed if using bit type instead.

 

[ymq8328]

I am a newbie in this field . I wiil use std_logic all the time, is this a good choice?

 

[SkyHigh]

Re: what is the diffirence between bit and std_logic In vhd

Not a good choice if you have to describe arithmetic and logical components like a multiplier.

Check "natural", "integer", "unsigned" and "signed" types. What do you think these types are introduced instead of std_logic for computation?

After you have checked these types, you might be able to answer yourself if using std_logic all the time is a good or bad choice for you.

 

[wjx197733]

I have the same experience of ymq8328. But multiplier is a digital circuit, Does "natural", "integer", "unsigned" and "signed" have any role in this circuit?

 

[rogertilman]

Re: what is the diffirence between bit and std_logic In vhd

First of all, these different types make writing, reading and understanding VHDL easier. I know it looks easier to use only one type "std_logic_vector" but the more complex a design gets with signed, unsigned, ranges and floating point the easier these differant types get.

 

[nittinsharma80]

Re: what is the diffirence between bit and std_logic In vhd

bit type has only two values: '0' or '1'

std_logic can have any value amongst :
'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care

these represnt different drive strenghts/resolved values

 

[soccer]

i think verilog is better than vhdl, why you try verilog?