# [SOLVED]What is the difference of power estimation between Design Compiler and PrimeTIme PX

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#### kkpark

##### Newbie level 2
Hello, I have a question about the method of power estimation.

I have two ways to estimate the power of my logic.
1) first one is from design compiler. When I synthesize the logic, a power report is generated in the directory of ./report... I think this does not use vcd file.
2) Second one is from primetime-PX using a vcd file. Before use PrimeTime, I generate the vcd file. After linking the vcd file and running PrimeTime, a detailed power report is generated.

Here is a quenstion. What is the difference of the power reports? I think the second way with the vcd file is more accurate, right? If right, is the first way with Design Compiler for estimating power not accurate or useless??

Additionally, the input vector to be tested in my logic is very massive. I think it is very difficult to cover or consider the countless input vector for estimating the power in my logic. Are there any appropriate or efficient methods for the estimation?

Thank you,
Sincerely,

#### jbeniston

Yes, you need to use a VCD file, otherwise the toggle count used for the power estimation is just a fixed value, and is unlikely to be the same as in your design. As dynamic power is proportion to the amount of toggling, this can result in widely inaccurate power estimates. You can read a VCD file in to Design Compiler though. (And it's worth doing this before you synthesize, so it can optimise based on the expected toggling)

kkpark

### kkpark

points: 2

#### wwfeldman

Additionally, the input vector to be tested in my logic is very massive. I think it is very difficult to cover or consider the countless input vector for estimating the power in my logic. Are there any appropriate or efficient methods for the estimation?
guesstimate the worst vectors for toggling, to get a reasonable power estimate.

test sections at a time, not the whole thing at once, to reduce test vector size and/or complexity.

kkpark

### kkpark

points: 2

#### kkpark

##### Newbie level 2
Thank you, jbeniston.

Thank you wwfeldman:smile:

The 'fixed' value of the estimated power is not an 'average expected' power in a logic. Right?
Then, when the estimated power from the first method could be used? (just curious about it, I will use the second method. Thanks))

Can I have one more question??
You said VCD file is read 'before' synthesis. Is the VCD file can be generated before synthesis? (I don't know much, sorry..)

The flow that I used to estimate power is ..
1. debug an RTL code using simvision.
2. Synthesize using Design Compiler.
3. Debug the logic (netlist from the synthesis) using simvision again. Compare the result with the result of step 1.
4. Generate VCD file using simvison. In this step, I choose an interval which I want to estimate.
5. Estimate power using the VCD file and PrimeTime.

Is there a way to estimate power more convenient?
I wonder how professional people do.

#### ThisIsNotSam

Something to consider is that you don't need to be very precise at logic synthesis stage, since there is still a long road to go before tapeout. A simplified VCD that only has the primary IOs can be used for a decent estimate. Later you can use a full-blown VCD for accurate power analysis, IR drop, dynamic power, etc.

kkpark

points: 2