Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Skew is the difference in insertion delay between two registers on a given clock domain...the clock domains can be different.
Useful skew is the concept of borrowing time from a register in a datapath, which has positive slack, to add to the launch register, which has negative slack thereby causing the entire path to meet timing. This is accomplished by adding delay to the clock of the register with positive slack.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.