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Latency is a term that is usually used with clocks .. clock latency is the delay between 2 points along one clock net .. in other words, if you consider a long clock net with some tab point along it .. then the delay between a certain point and another point on that net defines the latency ..
For the "Delay", it's a general word that works with any net .. it simply defines the total time consumed for the signal to move from the starting point of a net to the end point of that very net ..
The place where 'latency' and 'delay' become significant terms is in the physical design of your clock distribution network.
Before the clock distribution network is implemented (i.e. all steps up to and including placement), the clock distribution does not exist and is purely abstract. The clock signal is assumed to magically arrive at all the clock pins at the same time (with some uncertainty). This is called "ideal clock mode".
Once the clock network is actually created (usually with clock tree synthesis (CTS)), the clock signal can actually be timed exactly as it propagates from its source through a tree of buffers to every flip-flop. This is now called "propagated clock mode".
"Latency" is the term used to describe the delays on the clock distribution in ideal mode. There are usually 2 latencies that can be defined: the source latency and the network latency. The source latency is the delay specified to exist between the true source of the clock signal and when the lock signal arrives at the root clock pin in the design (so the true source is off-chip somewhere). This is used to specify the phase relationship between two clocks on the chip.
Network latency is the specified clock signal delay from the root clock pin to the flip-flop clock pins. This is not a measured delay - it is simply specified as part of the clock definition.
And so, "delay" in a clock refers to the actual measured delay in propagated clock mode. Source latency does not change when you build the clock - it always remains 'ideal' because it is off chip. The network latency, however, gets replaced by the "insertion delay". This is the actual, measured delay from the clock root to each individual flip-flop (usually it refers to the average insertion delay over all the FFs in the clock tree). Most CTS tools accept the network latency to be the desired insertion delay target that must be met. In the bottom-up design style, the network latency is often not specified or set to zero. This means the tool should do the best it can.
The question you asked is quite contextual. In what context do you want to know about the difference. For example if you are working with a particular tool it may mean different according to the definitions followed by that tool vendor. There is no absolute definition for these terms unless the context is specified.
In my experience, Latency is always generally used with the number of clock cycles it takes from the data entering a block to the time it leaves the block. Mostly logic designers and architects worry about Latency. It has no units but generally expressed as number of clock cycles.
Delay is generally the propagation delay of a signal through combinational logic. Its units are picoseconds or nanoseconds etc. Mostly Circuit designers and physical designers worry about delay.
In my experience, Latency is always generally used with the number of clock cycles it takes from the data entering a block to the time it leaves the block.
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