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hi,
Floor Planning concerns arrangment of modules and hard macros (if exist) in the core .
Placement concerns the placement of stanadrd cells present in module in the core area.
Floorplanning means arranging the Modules like ARM core, DSP core, Memory & etc.. in specific places whr it needs to be placed to optimize area & delay...
Placement describes how u r placing ur std.cells(And Gate, OR Gate &...) in the specific module...
Hi friends,i have gone through some books and wht i understand is,floorplanning is done before placement.during placement phase complete info of blocks r known,netlist,layout,interconnections etc.where as during floorplanning not complete info regarding the area,wiring area etc.
i.e., floorplanning arranging the flexible blocks where as placement is arranging the fixed blocks.
Floor Plan = designer decides how the hard macros ( RAM, ROM, Memories) r placed at different corners of the core...
Its done before placement..
Powerplanning is also included in it which is done with more calculations....
Placement = Placement is placing the top module on the core which consists of standard cells ( NAND, NOR, .etc )
Actually in floorplan stage , we try to explore various possiblities of placing a hard macro. after a few trials we will get rough idea of how to keep the hard macros so that we get optimum area,this is a plan phase where as the placement is the actual phase where you implement your plan.
Total wirelength: Minimizing the total wirelength, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength and wirelength squared, respectively. Timing: The clock cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay. Congestion: While it is necessary to minimize the total wirelength to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours. Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients.
A secondary objective is placement runtime minimization.[/b]
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