Re: One hot encoding
As amraldo write, this use one FF per state.
Using one-hot encoding use more FF, and more FPGA resources, but the benifit is that it can run at much higher speed.
Suppose the following example. Imagine that at:
State 1, you add 2 numbers.
State 2, you substract 2 other numbers.
State 3, you wait for some event, looping back to State 3 until event occur.
State 4, you send the results somewhere.
Now, this could use 2 FF to represent all 4 states (00, 01, 10 and 11). However, at the output of the FF, you will need a decoder for each of the states above. So, for state 1 (add 2 numbers), the adder hardware will first need to ensure that the FSM is in state 1, by using some logic gates to trigger when the 2 FF are '00'. Same for the subtracter, which will need some logic gate to trigger when the 2 FF are '01', and so on.
With one-hot encoding, instead of using 2 FF, you use 4 FF, one per state. So, FF #1 will be '1' when in state 1 (the other FF will be zero). FF #2 will be '1' when in state 2 (the other FF will be zero)... and so on. This way, the hardware adder, subtracter, ... doesn't need to have a decoder at input. It do the operation as soon as the FF output a 1.
This may first seem like both ways come to the same result, but if you look at timing, the state machine change state on clock transition. That is, the FF switch upon CLK input. However, since the one-hot encoding remove the need for state decoder, this meen that the hardware adder, subtractor, ... in the example above will output result faster (from clock transition to output result). This result in higher frequency limit for the FSM block.