What is the critical path in SRAM??

[vreddy]

Path in SRAM

wat is the critical path in SRAM??

critical path:------the logical path where the timing i s not met....

but how in SRAM?? can anyone discuss.......

thanks

 

[swamy.vlsi]

My friend had faced this question during an interview. The answer is as follows:

Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to charge ALL the gates of the pass transistors preceding the final column before the final column's pass transistors are asserted high. Likewise, after this process, when a 1 is read from this cell, it has to charge all all the parasitic capacitors in the entire column before charging the read / write buffer inpu

The critical path in an SRAM is the Read Operation. The bit line has to be discharged thro 2 transistors in series. Devices have to be sized to prevent the intermediate node from charging up too much. For the write operation, all constraints are automatically met by a large margin. Refer to Rabaey!:grin: