matrixofdynamism
Advanced Member level 2
Lets say I am writing VHDL code for a block that at runtime in hardware can be controlled to use a divided version of the clock. This could be div by 2, div by 4, div by 8 or div by 16 e.g a SPI master in FPGA.
I think that in theory, the following methods exist:
1. Use PLL with clock multiplexer to select one clock to drive the design.
2. Use gated clock with the gating signal coming from a counter.
3. Use clock enable with the enable signal coming from a counter.
Are there any other ways? While one can write VHDL code that will do the above in simulation, when it comes to creating an actual design, we need to be aware of how to do this correctly with the FPGA technology we are using since it will have some special primitives, IP, directives to the tool e.t.c to make the above happen.
Does anyone know how to correctly design hardware using VHDL or whatever is actually required, that effectively uses a divided version of the clock signal in Altera and Xilinx designs?
I think that in theory, the following methods exist:
1. Use PLL with clock multiplexer to select one clock to drive the design.
2. Use gated clock with the gating signal coming from a counter.
3. Use clock enable with the enable signal coming from a counter.
Are there any other ways? While one can write VHDL code that will do the above in simulation, when it comes to creating an actual design, we need to be aware of how to do this correctly with the FPGA technology we are using since it will have some special primitives, IP, directives to the tool e.t.c to make the above happen.
Does anyone know how to correctly design hardware using VHDL or whatever is actually required, that effectively uses a divided version of the clock signal in Altera and Xilinx designs?