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[SOLVED] What is the clock period of a differential clock?

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LatticeSemiconductor

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Hello all,

I am looking at the technical note for high-speed interfaces for a FPGA. It says that the pulse I have to provide can be assynchronous to the clock, but must be at least two clock cycles wide.

For me one clock cycle / period is this:

Code VHDL - [expand]
1
2
3
4
. _   _   _   _   _   _   _   _  
_| |_| |_| |_| |_| |_| |_| |_| |_
 
  from here  |<->|  to there



but this is for single ended clocks. In the technical note it shows the pluse width the same as above, so to me it is one clock period wide. It is considering a differential clock. I read elsewhere that a differential clock is designated as a two-phase clock, but I am not sure.

My question is, is the clock period of a differential clock different to a single ended clock (as per definition, i mean)? Or is it just an error on the technical note? Because i think the diagram shows the pulse width one clock period wide, and not two as it should be...

thanks
 

SunnySkyguy

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A differential clock has the advantage of twice the SNR and much better common mode rejection and low jitter with controlled balanced impedance.

A two phase clock that simply uses an inverter with same rising edge has some skew whereas a differential clock has less skew since delays are similar.

Actually this just 1 phase inverted and should not be confused with a 90 deg shift or quadrature 2 phase clock used for other applications.

If asynch. clock is used , it must be synch'd by receiver 2x clock , so async clock must be <= 1/2fmax or >= 2 periods wide.

That has nothing to do with single or differential.
 
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