LatticeSemiconductor
Member level 2
Hello all,
I am looking at the technical note for high-speed interfaces for a FPGA. It says that the pulse I have to provide can be assynchronous to the clock, but must be at least two clock cycles wide.
For me one clock cycle / period is this:
but this is for single ended clocks. In the technical note it shows the pluse width the same as above, so to me it is one clock period wide. It is considering a differential clock. I read elsewhere that a differential clock is designated as a two-phase clock, but I am not sure.
My question is, is the clock period of a differential clock different to a single ended clock (as per definition, i mean)? Or is it just an error on the technical note? Because i think the diagram shows the pulse width one clock period wide, and not two as it should be...
thanks
I am looking at the technical note for high-speed interfaces for a FPGA. It says that the pulse I have to provide can be assynchronous to the clock, but must be at least two clock cycles wide.
For me one clock cycle / period is this:
Code VHDL - [expand] 1 2 3 4 . _ _ _ _ _ _ _ _ _| |_| |_| |_| |_| |_| |_| |_| |_ from here |<->| to there
but this is for single ended clocks. In the technical note it shows the pluse width the same as above, so to me it is one clock period wide. It is considering a differential clock. I read elsewhere that a differential clock is designated as a two-phase clock, but I am not sure.
My question is, is the clock period of a differential clock different to a single ended clock (as per definition, i mean)? Or is it just an error on the technical note? Because i think the diagram shows the pulse width one clock period wide, and not two as it should be...
thanks