why to place clock gating near to the flop
Hi,
Clockgating is regulating the propagation of clock into a particular block.. suppose let us thing that there is a macro in chip which doesnot have any work for a long time.. then propagating clock to that module is a mere waste of power(as clock has the highest no.of transitions from 1 to 0 and vice versa.) so we will try to stop the clock propagation to that module.. we will resume the propagation of clock when it is needed..i.e, when the block is in use..how to do that? this is what is called as the concept of clockgating.. take a two-input AND gate and fix one input to clock and other to clk enable or chip enable (Assuming clk/chip enable is triggered at logic high). then the output of the AND gate is clk only when chip/clk enable is high otherwise always logic 0. This is known as clockgating..
One disadvantage od clock gating is the moment it passes thru AND/NAND gate, it will be treated a general toggling signal and clock buffers will nomore be inserted in its path.. So it is always advisable to have a clock gate very near to the block to which you want to do clockgating so that no more buffers are required inbetween.