What is the best way to reduce power for low power ASIC?

[jayakumarjay]

Re: LOW POWER ASIC

Is there any free tool for power analysis

can anyone help me

 

[haosg]

Re: LOW POWER ASIC

the simplest way is adding gated-clock in your RTL.
generally you can get 20%-40% power saving.

If you can cosider power in more high design stage, you can get more power saving.

don't rely on power-compiler.

 

[giggs11]

Re: LOW POWER ASIC

When it is said that power compiler tools like Power Compiler can be used to optimize power dissipation in a design, how is this done by the tool....?

Does the tool re-synthesize the logic to produce a more power efficient circuit...for instance like adding gated clockc...? Are there any other methods other than gated clock to optimize power at architectural or RTL level...?


Thanks

 

[Phantom]

Re: LOW POWER ASIC

Does anyone working on low power,

If yes which is the best way to reduce power


is by doing architectural analysis or gate level analysis

Use adiabatic logic.

 

[arunragavan]

Re: LOW POWER ASIC

as phantom mentioned adiabatic logic is ok to a certain extent --clock gating is also good.. DVS to the extent of algorithmic level .. but which is best when it comes to RTL abstraction..

I need to show the power consumed by each and every unit - to its RTL level and the entire unit as such...

any sugessions..

 

[abner]

Re: LOW POWER ASIC

Does anyone working on low power,

If yes which is the best way to reduce power


is by doing architectural analysis or gate level analysis

My idea is:
1. If your problem is peak power :
Use some power compiler or in apr stage to distribute your logic, make
logic not to toggle at same time.
2. If your problem is average power:
You can use
2.1 Low power cell from foundry
2.2 Use design to cover it ( gated clock ).
2.3 If your power budget is enough, re study your power lines to improve
power quality.

 

[tom123]

Re: LOW POWER ASIC

we should take power reduction measures in whole asic design flow,

from spec. to process.

this include architecture analysis and optimization,

gated clock in RTL, good floorplan for reducing parasitic capacitance,

low power process (use low Er insulator to reduce capacitance).

Does anyone working on low power,

If yes which is the best way to reduce power


is by doing architectural analysis or gate level analysis

 

[jjww110]

LOW POWER ASIC

turn off power is a better way than turn off clock somtimes!

 

[ee171]

Re: LOW POWER ASIC

just like jjww110 said, turn it off. if you don't use it, then it doesn't compsume power. how about switch VDD/VSS?

 

[funster]

Re: LOW POWER ASIC

The msthod to lower power include:

gating clock;

low power supply;

low wire connection's capacitance (by floorplan in backend);

best regards

Does anyone working on low power,

If yes which is the best way to reduce power


is by doing architectural analysis or gate level analysis

 

[laglead]

Re: LOW POWER ASIC

System and architecture optimization can lead to greatest power reduction.