When it is said that power compiler tools like Power Compiler can be used to optimize power dissipation in a design, how is this done by the tool....?
Does the tool re-synthesize the logic to produce a more power efficient circuit...for instance like adding gated clockc...? Are there any other methods other than gated clock to optimize power at architectural or RTL level...?
as phantom mentioned adiabatic logic is ok to a certain extent --clock gating is also good.. DVS to the extent of algorithmic level .. but which is best when it comes to RTL abstraction..
I need to show the power consumed by each and every unit - to its RTL level and the entire unit as such...
My idea is:
1. If your problem is peak power :
Use some power compiler or in apr stage to distribute your logic, make
logic not to toggle at same time.
2. If your problem is average power:
You can use
2.1 Low power cell from foundry
2.2 Use design to cover it ( gated clock ).
2.3 If your power budget is enough, re study your power lines to improve
power quality.