Re: LOW POWER ASIC
For dynamic power, the most immediate approach is to reduce the clock freuqency and supply voltage, although it may sounds obivious. That says, as far as power is concerned, deep pipelining can really burn out your chip. I think that's why Intel has given up their Jahwak (??) project due to unresolvable power dissipation issue. Just think that Intel has been pushing the clock frequency for so many years!
For static power, leakage power is the biggest problem, especially for portable applications. Your cell phone keeps on draining power even it's on standby mode! The common techniques to address leakage power is to embed high-th transistors on critical paths while low v-th transistor on non-critical paths (so called multi-threshold), or use sleep transistors to control the leakage. There're numerous papers talking about these.
As to the original question, I think designers focuses more on architectural level while gate level analysis is pretty much handled by EDA guys and the tools they made.