I ran across the systemverilog data type of 'logic' in the internet.
But I'm verilog user so systemverilog does not familiar with this.
So does anyone know the reasone that why we have to use logic instead reg of verilog data type?
reg and logic are synonyms. The use of the keyword reg is deprecated because it was used in places where no register is involved. See the middle of my post https://go.mentor.com/wire-vs-reg