A given technology should have an Abs Max rating that
is outside its performance-spec-basis range by a sane
margin. For example older logic families rated 4.5-5.5V
would have 6V or 7V abs max. But my experience inside
semiconductor companies tells me these ratings are often
ad hoc, often not even data based. You do not however
want to use Abs Max for something like load step which
can be a repetitive event - lying somewhere between
Rec Max (continuous, or per "use model") and Abs Max
(exceed once, and don't come crying to us with field
returns) bases. What you -should- do is allocate some
portion of the 5% tolerance to initial accuracy, steady
state PSRR and load deflection, some to aging, and some
to the load transients. But you may not like how tight those
shoes fit. Nonetheless, Rec Max is your budget, live within
your means.
A 2.2V input transient on load step means you have a
pretty lame supplier, or (perhaps more likely) a weak
input filter. You should design your local (POL) converter
with the assumption that the input source is inductive
(model it, if you can - apply load steps to that, and
look at current slew and voltage step). Look at the
current generation of integrated POLs for a better
option than a roll-your-own SMPS made of piece parts,
you can find some really good load-step response out
there (my designs, which you can't afford, had ~50mV
deflection on 8A load step (for a 10A rated part). The
larger players like TI, LTC, Intersil have good reference
designs for POL chips and often even offer "first inch"
layouts as apps collateral.
Quantifying your true worst case load step is also a
big deal, because this drives your design (over- or
under- being more likely, absent realism there).