What is the absolute maximum supply voltage spike withstand of ASICs?

[treez]

Hello,
We are designing a SMPS to supply an array of ASICs …..there are 200 ASICs and they are all powered from the 1V5 Bus. The maximum load current to these ASICs is 65A.
We still don’t know what will be the worst case load transient when these ASICs are all running. This could be a problem, as a full_load_to_no_load transient causes a spike of amplitude 2.2V on the supply Bus……..we don’t even know if repeated exposure to this kind of transient spike will damage the ASIC’s or not.
We had the ASICs custom made for us and they just told us to supply them with 1V5+/-5%.
So how can we find out what is the absolute maximum supply voltage spike withstand of these ASICs?

 

[KlausST]

Hi,

Best: Ask the manufacturer.

***
If it rises from 1.5V to 2.2V then this is more than 150% of the specified voltage. I doubt it is good for the ASIC.

But if it rises from 1.5V to 1.5V + 2.2V = 3.7V (wich isn´t clear to me) then i guess the ASIC won´t survive this for a longer time.

****

65A on a 1.5V line is difficult to handle.
The limit is 1.5V - 5% = 1.425V... means a voltage drop of 75mV.

If now the resistance (impedance for AC currents) from supply to ASIC is more than 1.1mOhm, then this causees the supply voltage to drop below specified minimum voltage.
Even when the voltage at the supply is rock solid ...

Therefore I tend to distributed power supplies.

Klaus

 

[ThisIsNotSam]

Hello,
We are designing a SMPS to supply an array of ASICs …..there are 200 ASICs and they are all powered from the 1V5 Bus. The maximum load current to these ASICs is 65A.
We still don’t know what will be the worst case load transient when these ASICs are all running. This could be a problem, as a full_load_to_no_load transient causes a spike of amplitude 2.2V on the supply Bus……..we don’t even know if repeated exposure to this kind of transient spike will damage the ASIC’s or not.
We had the ASICs custom made for us and they just told us to supply them with 1V5+/-5%.
So how can we find out what is the absolute maximum supply voltage spike withstand of these ASICs?

Ask the manufacturer. The transistor used for IO are usually huge and can stand ~5V, sometimes even 7V. They will age quicker, however.

 

[treez]

The transistor used for IO are usually huge and can stand ~5V, sometimes even 7V. They will age quicker, however.

Thanks, surely they are not "huge"? Sorry i do not understand which transistor you refer, you mean the little integrated transistors on the ASIC?

 

[ads-ee]

Huge is relative when you are talking about 14nm feature sizes ;-)

 

[dick_freebird]

A given technology should have an Abs Max rating that
is outside its performance-spec-basis range by a sane
margin. For example older logic families rated 4.5-5.5V
would have 6V or 7V abs max. But my experience inside
semiconductor companies tells me these ratings are often
ad hoc, often not even data based. You do not however
want to use Abs Max for something like load step which
can be a repetitive event - lying somewhere between
Rec Max (continuous, or per "use model") and Abs Max
(exceed once, and don't come crying to us with field
returns) bases. What you -should- do is allocate some
portion of the 5% tolerance to initial accuracy, steady
state PSRR and load deflection, some to aging, and some
to the load transients. But you may not like how tight those
shoes fit. Nonetheless, Rec Max is your budget, live within
your means.

A 2.2V input transient on load step means you have a
pretty lame supplier, or (perhaps more likely) a weak
input filter. You should design your local (POL) converter
with the assumption that the input source is inductive
(model it, if you can - apply load steps to that, and
look at current slew and voltage step). Look at the
current generation of integrated POLs for a better
option than a roll-your-own SMPS made of piece parts,
you can find some really good load-step response out
there (my designs, which you can't afford, had ~50mV
deflection on 8A load step (for a 10A rated part). The
larger players like TI, LTC, Intersil have good reference
designs for POL chips and often even offer "first inch"
layouts as apps collateral.

Quantifying your true worst case load step is also a
big deal, because this drives your design (over- or
under- being more likely, absent realism there).

 

[ThisIsNotSam]

Thanks, surely they are not "huge"? Sorry i do not understand which transistor you refer, you mean the little integrated transistors on the ASIC?

Oh no, course not. The small scaled transistors of modern nodes work in the 0.8-1.0V range. I am talking about the IO transistors, the ones used in the IO cells. They are huge in comparison with the transistors that actually implement the logic and they can withstand "big" voltages. Without going into much details, I can tell you ~5V is ok even for 16nm cutting edge silicon.

 

[treez]

Oh no, course not. The small scaled transistors of modern nodes work in the 0.8-1.0V range. I am talking about the IO transistors, the ones used in the IO cells. They are huge in comparison with the transistors that actually implement the logic and they can withstand "big" voltages. Without going into much details, I can tell you ~5V is ok even for 16nm cutting edge silicon.

...thanks, from this it sounds like trasients up to 2.2V or even more would be fine...as it appears that the only transistors that actually "see" this voltage are the bigger ones which can take 5V no problem?

 

[dick_freebird]

I don't think you understand the limits and where they
come from. It's not just "bigness" (L) but also the device
construction (Tox, spacer / halo / LDD). Your core devices
if they're rated for 1V, are for sure going to punch through
and maybe even latch up with 2.2V on them. The foundry
just isn't going to leave 2X voltage margin on the table,
when they could trade it for speed or density.

You need to get specific and get the foundry's ratings,
not generalities and quit trying to figure out what the
core VDD can be by looking at I/O devices, which are
different in a lot of ways (including things like guard
rings and such, which let them survive overstress that
the core is (rightly or not) believed not to be exposed
to.

 

[LISA_DALTON]

Hello,
We are designing a SMPS to supply an array of ASICs …..there are 200 ASICs and they are all powered from the 1V5 Bus. The maximum load current to these ASICs is 65A.
We still don’t know what will be the worst case load transient when these ASICs are all running. This could be a problem, as a full_load_to_no_load transient causes a spike of amplitude 2.2V on the supply Bus……..we don’t even know if repeated exposure to this kind of transient spike will damage the ASIC’s or not.
We had the ASICs custom made for us and they just told us to supply them with 1V5+/-5%.
So how can we find out what is the absolute maximum supply voltage spike withstand of these ASICs?

Rather than your question, I would be asking myself what can I do to tightly control the power supply output,
to the point of taking extreme measures. Only the manufacturer would be closest to being able to answer your original question, as they know how it was built. But, use ACTIVE semiconductor circuitry to squelch the spikes, and provide enough capacitance, with very low ESR, to fill in any sags.

 

[schmitt trigger]

You are skating on thin ice.........

You can do it the hard way, which essentially means testing a statistically valid amount of ASICs for a period of time, and with some acceleration factors (like temperature) applied.
By statistically valid, it would mean not only sufficiently large quantities but from different batches. There are many statistical tools which will allow you to predict failures in time.

The thing is, even if it passes the test, can you hold the ASIC vendor liable if the failure rate suddenly increases in the future?
Liability is a slippery slope, as a $1 component may impair a $1,000 module which forms part of a $1,000,000 machine.

My advice? Like Klaus has mentioned, there is a reason for distributed power and point-of-load converters. The reason being that maintaining tight regulation on a low voltage, high current, high current slew rate system is extremely challenging.
Even if you don't permanently damage the devices, the system may still crash.