synthesis xc_props
INIT attribute is used to generate LUT equation
here's a example from xilinx
Test case for using INIT attribute:
-- 4 input comparator with chip select example.
-- Given the signal DATA_IN (3 downto 0), the LUT equation is as follows:
~DATA_IN(3) * ~DATA_IN(2) * DATA_IN(1) * DATA_IN(0)
Library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity muxtest is port (
DATA_IN : in std_logic_vector ( 3 downto 0 );
CS : in std_logic;
CLK : in std_logic;
DATA_OUT : out std_logic );
end muxtest;
architecture structural of muxtest is
component LUT4
generic (INIT : bit_vector (15 downto 0) := b"0000000000000000");
port (
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic
);
end component;
component MUXF5
port (
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic;
O : out std_logic
);
end component;
component GND
port(
G : out STD_ULOGIC );
end component;
signal LUT_OUT: std_logic;
signal MUX_OUT: std_logic;
signal GND_IN: std_logic;
begin
MYLUT1: LUT4
generic map (
INIT => b"0000_0000_0000_1000"
)
port map (
I0 => DATA_IN(0),
I1 => DATA_IN(1),
I2 => DATA_IN(2),
I3 => DATA_IN(3),
O => LUT_OUT
);
MYMUXF5: MUXF5 port map (
I0 => LUT_OUT,
I1 => GND_IN,
S => CS,
O => MUX_OUT
);
MYGND: GND port map ( G => GND_IN );
process ( CLK )
begin
if ( CLK = '1' and CLK'event ) then
DATA_OUT <= MUX_OUT;
end if;
end process;
end structural;