Re: Bias
The input ("Vin+" - "Vin-") to the differential pair are either in ECL logic or some form of logic signal, the input should be large enough to switch the differential pair.
I think the tail current (Mdiffbias) of the differential pair is two times the current in the MP1 and MP2. (based on the schematic is seem that there are some errors, the Id current in Mdiffbias is the same as the MP1 and MP2, mouzid please check this) .
Assuming Id current in MP1 is I and the capacitors seem in the Vout- and Vout+ nodes are the same, it is equal to Cds of MP1 + Cds of the differential + the cload of the next stage. The delay is controlled by the current I as output voltage swing will depends the current is need to charge the capacitance in the Vout- or vVout+ nodes.
To control the amount of current charging the capacitance in the output node, the Vcont voltage controls the bias current. Thus the delay can be controlled by Vcont voltage.
Increase the Vcont voltage will shorten the delay, similarly decrease the Vcont voltage will increase the delay.