What is race condtion?

W_Heisenberg · Jan 16, 2012

Is race condtiion caused by propagation delay?

How do we determint the propagation delay for a logic element?

Anyone can point this out?

shaiko · Jan 16, 2012

W_Heisenberg said:
Is race condtiion caused by propagation delay?

Yes, but not only. combinatorial logic also causes delays.

W_Heisenberg said:
How do we determint the propagation delay for a logic element??

The propagation delay is process dependent - 45nm technology will have less delay than 90nm and so on...

krishna2728 · Jan 17, 2012

WWW.TESTBENCH.IN - Verilog for Verification

Verilog Technical Tidbits

see these links can be helpful for you

cks3976 · Jan 17, 2012

Race condition is mainly an incorrect implementation of logic, or incorrectly handled default cases of a switch. Propagation delay might, or m,ight not really contribute to race condition.
If the logic element is a part of standard cell library you will get the propagation delay as a part of its specification. Else you will need to calculate the same if this is a custom design block.

W_Heisenberg · Jan 17, 2012

I see:-o

thanks

What is race condtion?

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