What is procedure of PLL design?

[rose_song]

working procedure of pll

What is procedure of PLL design?

 

[eesoko]

procedure to design pll

1. Learn what each part of PLL does.
2. Get the specs (this will define topology and specs for each part of the loop)
3. System level (I recommend simulink)
4. Behavioural modeling (Either simulink or veriloga)
5. Replace veriloga models with actual schematics, in case that you use Cadence for design.
6. Don't go crazy.

Each step is followed with lots of reading (even the first one ).

 

[flyinspace]

A lot of work to design PLL.
So the better way is to refer the other's old design.

 

[uncle_urfi]

Goto national.com and type

easypll

this brings up the simulator and the links.
Also search for Dean Bannerjee's book on the same website for PLL design.

 

[swicap]

is the result of the easypll trustworthy?

 

[uncle_urfi]

The people at National will claim that the results are okay, as long as you use the parts suggested by their application notes.

Try Fujitsu's website as well.
and CircuitSage : http://www.circuitsage.com/pll.html
and Deisgner's guide: http://www.designers-guide.com/

And try other simulators as well, if you have access to them.

=PLL= from eagleware is one example. www.eagleware.com.

I wouldn't suggest using HPADS since it is too complicated and is appropriate for much larger projects. But if you already know the tool, it would be worthwhile trying.


With SpectreRF there is a PLLlib that has builtin behavioral models.

In order to learn how to design PLLs, try the Synthesizer Design Course offered by Prof. P.E. Allen at Georgia tech.

Have fun.