1. Learn what each part of PLL does.
2. Get the specs (this will define topology and specs for each part of the loop)
3. System level (I recommend simulink)
4. Behavioural modeling (Either simulink or veriloga)
5. Replace veriloga models with actual schematics, in case that you use Cadence for design.
6. Don't go crazy.
Each step is followed with lots of reading (even the first one ).
I wouldn't suggest using HPADS since it is too complicated and is appropriate for much larger projects. But if you already know the tool, it would be worthwhile trying.
With SpectreRF there is a PLLlib that has builtin behavioral models.
In order to learn how to design PLLs, try the Synthesizer Design Course offered by Prof. P.E. Allen at Georgia tech.