what is meant by logic optimization?

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for example,

using k-map or Quine–McCluskey algorithm to reduce the logic. There are other algorithms too.

Remember to google first
 

Hi all,

when perform Logic optimization in tools what happens ?


Thanks.........
 

Logic optimization, a part of logic synthesis, is the process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. Generally the circuit is constrained to minimum chip area meeting a pre-specified delay.

https://en.wikipedia.org/wiki/Logic_optimization
eia.udg.es/~forest/VLSI/lect.05.pdf
 

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