1) there is no maximum speed - it will depend on your design and routing resources.
2) It depends how much memory is available in the device. Often, a longer capture window means you can view less signals.
3) That will be proprietary and I dont think XILINX will tell you what it is.
how fast changing are you talking about?
usually you just use the same clock as the "fast changing" signals. You can use a faster clock if you need to, but you're never going to see it perfectly.
as TrickyDicky said - chipscope uses the clock you've connected to it;
you can connect any clock of your design you wish;
chipscope is just a module - same as a module written by you,
but 'prepeared' by an fpga vendor;
so it's up to you what signals this module monitors and with
what clock it runs;
also the max. chipscope clock frequency depends - as in 'normal'
design - on complexity of the whole project, your logic + the monitoring logic;
[the chipscope]
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J.A
I'd say it is directly proportional to your flipflop clock. If you use 300MHz clock, you can watch flipflop value changing at 300MHz rate. No doubt.
But remember, that this is true only for synchronous designs. If you want to capture asynchronous signal namely asy_sig, say at 2MHz, then your sampling/trigger clock shall be at aleast 20 MHz to watch asy_sig toggling. Otherwise, you will miss the exact edges of asy_sig.
But this is yet not accurate. Instead you can keep rising edge trigger of asy_sig and then capture the signal for good timing results.
The higher the trigger clock, the better the waveforms.