What is low power vlsi design

[satyakumar]

Hi all,
Can any body tell me what is low power vlsi design, with example is very help full for me.
thanks to all

 

[incisive]

Low power Design :

power = static + dynamic power.

Dynamic power can be reduced in gate level as well as architecture/design, coding level(for small portion).

example -- coding - using one-hot encoding for state machines,
-- Using gate enabled clocks for ff's
there r many other ways where u need to compromise with area and other stastics to achieve a low power design.

 

[satyakumar]

Hi,
Interms coding u r explaination is corect, if we take a flip flop at circuit level. How one can design for low power.

 

[incisive]

well there ae three levels of achieving low power

RTL level

architectural level

algorithmic level

most popular is the algorithmic level of achieving low power.

there are some methods like

clock gating
signal gating
reduting switching activity - transistor sizing, progressive transistor sizing, input reordering, time multiplexing resources and logic restructing.
adiabatic computing - reduce the voltage swings
dynamic voltage scaling - reduce the threshold voltageuse of low power busses - low sing busses..

reducing the voltage swing can help us reduce the power consumed.
these are a few ways to achieve low power of operation.

 

[vlsi_whiz]

Low Power design can be for both Digital Design as well as Analog Design.

For Digital Design, as stated earlier..it translates to - System level, Architecture level ,logic level, RTL Level,etc...

In the case of Analog Design, we have low power techniques in device level, architecture level. Device level techniques include use of MOSFETs such as SOI MOSFETs, DT-MOSFETs and others. SOI MOSFETs reduce leakage power and hence lower the power consumption. DT-MOSFETs (Dynamic Threshold) are devices where the Threshold voltage (Vt) of the transistor is varied such that the transistor switches ON and OFF faster and for lower voltages.

At the architecture level, in analog design, we have various architectures for low-power, high-speed such as low-power CMOS OPAMP, high-speed OPAMPs. In the case of the D-FF also, here at the ckt level, we would choose between using SOI, DTMOS and check the power consumption and also we would try out new ckt topologies for low power.

 

[satyakumar]

Hi,
Nice expalination, i have still some doubt. In all these methods there is trade of b/w power and other parameters like speed, area,. etc. I want to know is there any way with out influencing other parameters.

 

[research235]

Hello satya ..

please go through any of the low power VLSI design material, u will know more in details, Using clock gating for dynamic power reduction we infact reduce the over all area as a grp of mux r replaced by a sigle driven CGckt circuit.

So any uni lecture slides will help u inunderstanding this better , let me know if u need any materials

suresh

 

[incisive]

Optimization Method
Power-Saving Percentage

Algorithm Level
75%

Architecture Level
50%–75%

Register Transfer Level
15%–50%

Gate Level
5%–15%

Transistor Level
3%–5%

PDynamic = 1/2.n.B.C.Vdd.Vdd.F


various factors involved in saving dynamic power

ß
Saves power by optimizing the excessive transitions through clock gating

C
Saves power by using an appropriate process technology or improving the layout

VDD
Saves power dramatically but slows down the circuit

F
Saves power through reducing the clock frequency but results in slowing down the functionality



In order to minimize power in the gate level, load capacitances should be minimized by using less logic. Low-power EDA tools usually handle this as part of their optimization techniques. Here, gate minimization is achieved using proper Boolean functions, followed by appropriate use of don't cares in Karnaugh maps (K-maps).

 

[satyakumar]

Hi suresh,
Can you post some material on low power vlsi design

 

[maharshi_qis]

total power consumption by a ckt = static power + dynamic power
static power would be due to leakage and dynamic power is during switching time..
if clk speed is high,n faster switching then dynamic power is more...
if low dielectric is used as oxide ,n static power is more.........
designing a ckt by reducing these powers is called low power vlsi design....

 

[research235]

low power VLSI design

 

[eexuke]

Hi incisive,
How can you derive these numbers such as "Algorithm Level 75%" ? Is there any document or book that deals with how to estimate power reduction on different design levels?

 

[ftfs2002]

oh thanks everyone ,i have benefited it very much