Low Power design can be for both Digital Design as well as Analog Design.
For Digital Design, as stated earlier..it translates to - System level, Architecture level ,logic level, RTL Level,etc...
In the case of Analog Design, we have low power techniques in device level, architecture level. Device level techniques include use of MOSFETs such as SOI MOSFETs, DT-MOSFETs and others. SOI MOSFETs reduce leakage power and hence lower the power consumption. DT-MOSFETs (Dynamic Threshold) are devices where the Threshold voltage (Vt) of the transistor is varied such that the transistor switches ON and OFF faster and for lower voltages.
At the architecture level, in analog design, we have various architectures for low-power, high-speed such as low-power CMOS OPAMP, high-speed OPAMPs. In the case of the D-FF also, here at the ckt level, we would choose between using SOI, DTMOS and check the power consumption and also we would try out new ckt topologies for low power.