what &&& is it in verilog...

cyhuang056 · May 30, 2007

verilog &&&

i don't understand &&& in verilog...
plz tell me.
what does it mean?
thanks~

rajsrikanth · May 30, 2007

&&& verilog

Conditional timing checks (using the &&& notation) are made only if the
condition is true.

pravi · Jun 1, 2007

&&& in verilog

&&& is a Verilog 2001 operator, but it is only used for timing_check_conditions in timing_check_events

shiv_emf · Jun 3, 2007

what does &&& means in verilog

pravi said:
&&& is a Verilog 2001 operator, but it is only used for timing_check_conditions in timing_check_events

can u put it in other words..

timing_check_conditions?

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