what &&& is it in verilog...

[cyhuang056]

verilog &&&

i don't understand &&& in verilog...
plz tell me.
what does it mean?
thanks~

 

[rajsrikanth]

&&& verilog

Conditional timing checks (using the &&& notation) are made only if the
condition is true.

 

[pravi]

&&& in verilog

&&& is a Verilog 2001 operator, but it is only used for timing_check_conditions in timing_check_events

 

[shiv_emf]

what does &&& means in verilog

&&& is a Verilog 2001 operator, but it is only used for timing_check_conditions in timing_check_events

can u put it in other words..

timing_check_conditions?