What is High-Z do to scan-in in DFT?

[liuzhili]

when will scan out go to highz states

I found that some High-Z input to scan-in port in a DFT stil/wgl file, what will ATE do when pattern in High-Z?
I think High-Z means not connected, and that means the input port is floating, and after a gate(like NOT or AND logic) it must be High-Level(Digital 1) or Low-Level(Digital 0), and this is not stable because floating, then will cause scan-out unstable unless this High-Z input does not matter with 1 or 0.
but I try to replace scan-in High-Z with 1 or 0,founding scan-out in some shift-phase compare will come error. So I want to know what is High-Z do? why High-Z can't replaced by 1 or 0 in scan-in port?
Any one who knows please tell me why, Thanks

 

[joe2moon]

high-z pin test

High-Z means not driving.

So maybe it has been driven by other source. This port might be multi-driven one.

Therefore, if you force it to logic-1 or logic-0, then results in conflict.

 

[liuzhili]

what is high z logic

In my simulation. all pins for test is driven by one source outside the chip, How may/can other driven come from in that situation?Could you give me an example?

 

[XHL]

test highz

Hi,

If you leave the scan in as High-Z, does your atpg sim pass?

Please make sure it's the High-Z input cause the issue or it's another issue caused by internal scan paths.

 

[Vmanthapuri]

what is highz

One of the possibilty cud be that " the perticular pin is BIDI". By defning the input as high Z I.e. high impedence you are telling the ATE to not to drive tht perticular PIN.
This is what fastscan does when you constrain a BIDI pin as PO only using "ADD PIN CONSTRAINT" command.
apart from that the other possibility could be that your "ATE" has the capability to detect the difference b/w logical 0 and high impedence values(which very few testers can do) so your patterns contain high z values too.
Hope it helps,
~V

 

[liuzhili]

Hi,

If you leave the scan in as High-Z, does your atpg sim pass?

Please make sure it's the High-Z input cause the issue or it's another issue caused by internal scan paths.

In my simulation, the scan in ports are connected to a stimulator module, the stimulator module assign value from stil/wgl file, and the stil/wgl scan in ports contains "Z", so the DUT scan in ports are driven by "Z". and after run simulation with vcs and the dumpped waveform also show the scan in is driven by "Z"

With High-Z to scan in ports, the simulation worked welll and the scan out value check is also correctly.
But when I try to insert a FILTER module between stimulator and DUT's scan-in ports, run simulation with vcs, some of the scan out value is not the same as stil/wgl, and the FILTER module only do:
OUT=((IN===1'bX) || (IN===1'bZ))?1:IN;

Added after 29 minutes:

One of the possibilty cud be that " the perticular pin is BIDI". By defning the input as high Z I.e. high impedence you are telling the ATE to not to drive tht perticular PIN.
This is what fastscan does when you constrain a BIDI pin as PO only using "ADD PIN CONSTRAINT" command.
apart from that the other possibility could be that your "ATE" has the capability to detect the difference b/w logical 0 and high impedence values(which very few testers can do) so your patterns contain high z values too.
Hope it helps,
~V

YES, in my design, scan-in and scan-out ports are bidirectory ports in functional mode not scan mode, and like functional bidirectory port BIDI_IN defined scan-in port when in scan mode and functional bidirectory port BIDI_OUT defined as scan-out port.
so I think in scan mode, the BIDI_IN is only input and BIDI_OUT is a output, right?
and this is why I change stil/wgl scan-in "Z" to 1 because I think in real DFT test PCB board, High-Z input means float and also unstable. because in test mode scan in port also driven by one source. and even more I think if High-Z input is OK, mease float is OK, if float into a digital logic cell , the logic cell treat it as Low/High Logic in and output as a certain Logic High/Low value, and the high-Z as Low/High Logic input is uncertain/unstable, and why can't I drive it by a certain value and come out error? and I'v very afraid that in a real phisical test PCB board, the high-Z input will make the test result very unstable.

 

[maiez]

Hi,

I think for BIDIR pins, you can't switch directly from input to output mode (or vise versa), so the High-Z state is put to be sure that the transition is well done.
This is what I understood from the testcases I've manipulated.

Thanks and regards.

 

[pavankumarmnnit]

hi freinds , i am having problem regarding high -Z in my design .My design is not able to be synthesized in design compiler . In my design i need to block some ports for some condition .my raw code is like below .The situation is when some port is in Z impedance some operation should be done (in dc the conditional statements are shown as error) .please suggest alternative

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bproc is
port(a,b:in std_logic_vector(2 downto 0);clk:in std_logic;sin1,sin2:inout std_logic_vector(2 downto 0):="ZZZ";
i:in std_logic_vector(1 downto 0);c,dut std_logic_vector(2 downto 0);
sftloadbar1 :inout STD_LOGIC;
testnormalbar1 :inout STD_LOGIC;
blockout1:inout std_logic;
serblocken1:inout std_logic;
serouten1:inout std_logic;
sftloadbar2 :inout STD_LOGIC;
testnormalbar2 :inout STD_LOGIC;
blockout2:inout std_logic;
serblocken2:inout std_logic;
serouten2:inout std_logic;
y:in std_logic;reconfig1,reconfig2:in std_logic;
reload:in std_logic_vector(2 downto 0));
end bproc;

architecture Behavioral of bproc is
signal k,l: std_logic:='0';
signal a1,b1:std_logic:='0';
begin
U1rocess(a,b,clk,i,sin1,sin2,y)
variable s1,s2,s3,s4:std_logic;
begin
case i is
when "00"=>s1:=a(2);s2:=b(2);s3:=sin1(2);s4:=sin2(2);
when "01"=>s1:=a(1);s2:=b(1);s3:=sin1(1);s4:=sin2(1);
when "10"=>s1:=a(0);s2:=b(0);s3:=sin1(0);s4:=sin2(0);
when others=>s1:='Z';s2:='Z';s3:='Z';s4:='Z';
end case;
if(clk'event and clk='1')then
c<=a;
d<=b;
--1st one
if(reconfig1='0' and s1='1')then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='1';
blockout1<='1';
serblocken1<='0';
elsif(reconfig1='1' and y='0' and a1='0')then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='1';
blockout1<='0';
serblocken1<='1';
a1<='1';
elsif(s1='0' and s3='0' and y='0')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='0' and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='1' and y='0')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='1'and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='1' and s3='Z' and y='0')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='Z' and y='0')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='1';
blockout1<='0';
serblocken1<='1';
elsif(reload="ZZZ" and y='1') then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='0' and s3='Z' and y='1' and k='0')then
sftloadbar1<='0';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
k<='1';
elsif(s1='0' and s3='Z' and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='0';
serblocken1<='0';
elsif(s1='Z' and s3='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='1';
serblocken1<='0';
elsif(s1='Z' and s3='0' and y='0')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
elsif(s1='Z' and s3='0' and y='1')then
sftloadbar1<='1';
testnormalbar1<='0';
serouten1<='0';
blockout1<='1';
serblocken1<='0';
elsif(s1='Z' and s3='Z')then
sftloadbar1<='1';
testnormalbar1<='1';
serouten1<='1';
blockout1<='0';
serblocken1<='0';
end if;
--2nd one
if(reconfig2='0' and s2='0')then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='1';
blockout2<='1';
serblocken2<='0';
elsif(reconfig2='1' and y='0' and b1='0')then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='1';
blockout2<='0';
serblocken2<='1';
b1<='1';
elsif(s2='0' and s4='1')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='0' and y='0')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='0' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='1' and y='0')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='1' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='Z' and s4='0')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='1';
serblocken2<='0';
elsif(s2='Z' and s4='1' and y='0')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(reload="ZZZ" and y='1') then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='Z' and s4='1' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='1';
serblocken2<='0';
elsif(s2='0' and s4='Z' and y='0')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='Z' and y='0')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='1' and s4='Z' and y='1' and l='0')then
sftloadbar2<='0';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
l<='1';
elsif(s2='1' and s4='Z' and y='1')then
sftloadbar2<='1';
testnormalbar2<='0';
serouten2<='0';
blockout2<='0';
serblocken2<='0';
elsif(s2='Z' and s4='Z')then
sftloadbar2<='1';
testnormalbar2<='1';
serouten2<='1';
blockout2<='0';
serblocken2<='0';
end if;
end if;
end process U1;
end behavioral;

 

[pete_lu]

I found that some High-Z input to scan-in port in a DFT stil/wgl file, what will ATE do when pattern in High-Z?
I think High-Z means not connected, and that means the input port is floating, and after a gate(like NOT or AND logic) it must be High-Level(Digital 1) or Low-Level(Digital 0), and this is not stable because floating, then will cause scan-out unstable unless this High-Z input does not matter with 1 or 0.
but I try to replace scan-in High-Z with 1 or 0,founding scan-out in some shift-phase compare will come error. So I want to know what is High-Z do? why High-Z can't replaced by 1 or 0 in scan-in port?
Any one who knows please tell me why, Thanks

Generally speaking, High-Z input should not appear in stil/wgl file. One exception is
BIDI pin, force first cycle as High-Z to make it uni-directional.
And notice that High-Z is different from 0/1, so if you modifiy the High-Z input as 0/1, scan-out compare will come error. But X is same as 0/1 value.
So to solve the problem, please add "set buses -external_z X" in your script, and it will prevent generation of unexpected Z value.
Hope it helps!