Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what is ground bounce and how to elimate it?

Not open for further replies.
ground bounce means the 0V power net is not 0V in your chip/board, some noise on you power net.
using de-coupling cell in your chip

Ground bounce is due to rapid current sink/source thru bonding wire between ground pad and package pin. dV= L(dI/dt)
SO the methods to mitigate this ground bouncing effect are:
(1) lower the inductance(L):
for example; double/triple bonding for groung pin. or using flip-chip packaging, ...,etc.
(2) lower the current spike(dI/dt):
for example; using slew-rate control output buffer, decoupling cap in internal power-gnd net, well controlled slew-rate of internal signal with adequate buffer size, ..., etc.

Hope it helps :)

Kindly see the attachment.




power network layout maybe import , power pad numbers also needs consideration.

Experience from the trenches say, the easiest way out is :

Pulling appropriate caps near the ground pins of each IC and enough provision for copper pour dedicated to ground.

hi murali
i didnt got any attachment from u r side. plz send me attachment


Ground bounce is a phenomenon associated with transistor switching where the gate voltage can appear to be less than the local ground potential, causing the unstable operation of a logic gate.

Not open for further replies.

Part and Inventory Search

Welcome to