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Sometimes you need to flatten a PCELL in order to edit it to fit in an odd shape. PCELLs are the standard layout views that you instance from your technology library. For instance, if you instance a PMOS from your library, you are unable to edit the shape of the cell. Flattening is often used in digital design where you would like to minimise the size of the circuit as much as possible. In analog design, flattening is not used as much because it can decrease the performance of the transistor. As for the lec check that you are speaking of, I have no idea.
I don't know for sure. The following seems obvious.
In most general meaning flattening means ungrouping hierarchy and bringing all components on the first level of hierrachy. For example if you had a circuit like [ [A B ] [ C D [E] ] ] that will become [ A B C D E ]. in LEC it is needed to be able to check equivalence, because hierarchy can be different where function can be the same.
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