Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The DC's default Static timing Analyzer (STA) engine is Nautilus Delay Analyzer. It's slower and lower performace than PT's STA.
And there're 2 version of PT call PT-overlay and PT-stand alone .
PT - overlay let u to install PT STA in DC directory and overlay with DC.
For the most timing consuming operation in search muliple paths by -from
-through -to , it had better run in PT. DC often run into a endless loop and
can not handle this.