What is DIBL effect? How it affects MOS modelling?

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what is dibl

What is DIBL ( Drain Induced Barrier Lowering ) Effect?. How this has been taken care while modelling MOS?.
 

dibl current

Ideally , Drain current Ids should be Constant (Independent of Vds) in Saturation Region.
In Reality , Ids increases with Vds in saturation region . Its Bcoz of atleast 2 reasons.

1) CLM (Channel Length Modulation)
As Vds increases , Length Leff decreases , hence current increases

2) DIBL (Drain Induced Barrier Lowering)
As Vds increases , Vt decreases , hence current increases

D in DIBL word refers to Vds (Drain Voltage)
B in DIBL word refers to Vt (Threshold Voltage)

so "Drain Induced Barrier Lowering" means "Vds induced Vt Lowering" .

just like Networking folks like three letter Acronyms (TLAs) , even circuit designers like fancy acronyms with cool pronounciations (pronounced Dibble) for PhD Thesis!.
 
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